Integrated circuits, including dies, for example, imager dies such as charge-coupled-devices (CCD) and complementary metal oxide semiconductor (CMOS) dies, have commonly been used in image reproduction applications.
Imager dies, such as the CMOS imager die, typically contain thousands of pixels in a pixel array on a single chip. Pixels convert light into an electrical signal that can then be stored and recalled by an electrical device such as, for example, a processor. The electrical signals that are stored may be recalled to produce an image on, for example, a computer screen or a printable media.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630; 6,376,868; 6,310,366; 6,326,652; 6,204,524; 6,333,205 each of which being assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a block diagram of an imager die 10, having a CMOS imager device 8. The CMOS imager device has a pixel array 14 that comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixel cells of each row in pixel array 14 are all turned on at the same time by a row select line, and the pixel cells of each column are selectively output by respective column select lines. A plurality of rows and column lines are provided for the entire pixel array 14. The row lines are selectively activated in sequence by the row driver 1 in response to row address decoder 2 and the column select lines are selectively activated in sequence for each row activation by the column driver 3 in response to column address decoder 4. The CMOS imager device 8 is operated by the control circuit 5, which controls address decoders 2, 4 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 1, 3 to apply driving voltage to the drive transistors of the selected row and column lines.
The pixel output signals typically include a pixel reset signal Vrst taken from a charge storage node when it is reset and a pixel image signal Vsig, which is taken from the storage node after charges generated by an image are transferred to the node. The Vrst and Vsig signals are read by a sample and hold circuit 6 and are subtracted by a differential amplifier 7, which produces a difference signal (Vrst−Vsig) for each pixel cell, which represents the amount of light impinging on the pixels. This signal difference is digitized by an analog-to-digital converter 9. The digitized pixel difference signals are then fed to an image processor 11 to form a digital image. In addition, as depicted in FIG. 1, the CMOS imager device 8 may be included on a single semiconductor chip to form the imager die 10. The imager die 10 can be included in a number of image reproduction applications, including, but not limited to, cameras, personal digital assistants (PDAs), scanners, facsimile machines, and copiers.
Users often desire to see images full of contrast in image reproduction applications, such as, for example, a photograph. Such images are visually pleasing because they look lively, clear and have lots of details. Known methods for contrast improvement include modifying transfer function (“s-curve”), contrast stretching, histogram equalization, and amplifying luminance component. Each method has its own drawbacks, which may result in poor image quality.
Accordingly, there is a desire and need for processing an image to increase the contrast of the image, without adversely affecting the visual quality of the image.